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ds05-11309-1e fujitsu semiconductor data sheet memory cmos 1 m 4 bits hyper page mode dynamic ram mb814405d-60/60l/-70/70l cmos 1,048,576 4 bits hyper page mode dynamic ram n description the fujitsu mb814405d is a fully decoded cmos dynamic ram (dram) that contains 4,194,304 memory cells accessible in 4-bit increments. the mb814405d features the ?yper page mode of operation which provides extended valid time for data output and higher speed random access of up to 1,024 4 bits of data within the same row than the fast page mode. the mb814405d dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb814405d is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb814405d is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb814405d are not critical and all inputs are ttl compatible. n product line & features parameter mb814405d -60 -60l -70 -70l ras access time 60 ns max. 70 ns max. cas access time 15 ns max. 20 ns max. address access time 30 ns max. 35 ns max. random cycle time 105 ns min. 125 ns min. hyper page mode cycle time 25 ns min. 30 ns min. low power dissipation operating current normal mode 495 mw max. 413 mw max. hyper page mode 385 mw max. 358 mw max. standby current ttl level 11 mw max. 8.25 mw max. 11 mw max. 8.25 mw max. cmos level 5.5 mw max. 1.1 mw max. 5.5 mw max. 1.1 mw max. 1,048,576 words 4 bits organization silicon gate, cmos, advanced-stacked capacitor cell all input and output are ttl compatible 1,024 refresh cycles every 16.4 ms self refresh function this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. standard power and low power versions early write or oe controlled write capability ras -only, cas -before-ras , or hidden refresh hyper page mode, read-modify-write capability on chip substrate bias generator for high performance
2 mb814405d-60/60l/-70/70l n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.0 to +7.0 v voltage of v cc supply relative to v ss v cc ?.0 to +7.0 v power dissipation p d 1.0 w short circuit output current i out ?0 to +50 ma storage temperature t stg ?5 to +125 c package and ordering information ?26-pin plastic (300 mil) soj, order as mb814405d- pjn ?26-pin plastic (300 mil) soj, order as mb814405d- lpjn (low power) plastic sof package (lcc-26p-m04)
3 mb814405d-60/60l/-70/70l n capacitance (t a = 25 c, f = 1 mhz) parameter symbol typ. max. unit input capacitance, a 0 to a 9 c in1 ?pf input capacitance, ras , cas , we , oe c in2 ?pf input/output capacitance, dq 1 to dq 4 c dq ?pf ras a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 cas we oe v cc v ss dq 1 to dq 4 fig. 1 ? mb814405d dynamic ram - block diagram clock gen #1 write clock gen mode control clock gen #2 column decoder sense ampl & i/o gate 4,194,304 bit storage cell data in buffer data out buffer address buffer pre- decoder refresh address counter row decoder substrate bias gen & a 9
4 mb814405d-60/60l/-70/70l n pin assignment and description designator we oe function ras row address strobe write enable output enable a 0 to a 9 address inputs v cc +5.0 volt power supply v ss circuit ground cas column address strobe 26-pin soj (top view) 1 2 3 4 5 14 15 16 9 10 11 12 13 26 25 24 23 22 18 17 we oe cas v ss v cc a 0 a 1 a 2 a 3 a 9 a 8 a 7 a 6 a 5 a 4 dq 4 dq 3 ras dq 2 dq 1 dq 1 to dq 4 data input/output
5 mb814405d-60/60l/-70/70l n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs twenty input bits are required to decode any four of 4,194,304 cell addresses in the memory matrix. since only ten address bits are available, the column and row inputs are separately strobed by cas and ras as shown in figure 5. first, ten row address bits are input on pins a 0 -through-a 9 and latched with the row address strobe (ras ) then, ten column address bits are input and latched with the column address strobe (cas ). both row and column addresses must be stable on or before the falling edge of cas and ras , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways?n early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or cas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data (dq 1 to dq 4 ) is strobed by cas and the setup/hold times are referenced to cas because we goes low before cas . in a delayed write or a read-modify-write cycle, we goes low after cas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs and high-z state are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : from the falling edge of cas when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max), and t rcd (max) is satis?d. t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa. t oez : from oe inactive. t off : from cas inactive while ras inactive. t ofr : from ras inactive while cas inactive. t wez : from we active while cas inactive. the data remains valid after either oe is inactive, or both ras and cas are inactive, or cas is reactived. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage *1 v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 000 input high voltage, all inputs *1 v ih 2.4 6.5 v input low voltage, all inputs* *1 v il ?.0 0.8 v input low voltage, dq* *1 v ild ?.0 0.8 v
6 mb814405d-60/60l/-70/70l hyper page mode operation the hyper page mode operation provides faster memory access and lower power dissipation. the hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each page of memory (within column address locations), any of 1,024 4-bits can be accessed and, when multiple mb814405ds are used, cas is decoded to select the desired memory page. hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. hyper page mode features that output remains valid when cas is inactive until cas is reactivated.
7 mb814405d-60/60l/-70/70l n dc characteristics (at recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol conditions value unit min. typ. max. std power low power output high voltage *1 v oh i oh = ?.0 ma 2.4 v output low voltage *1 v ol i ol = 4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in 5.5 v; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i o(l) 0 v v out 5.5 v; data out disabled ?0 10 operating current (average power supply current) *2 mb814405d-60 i cc1 ras & cas cycling; t rc = min ma mb814405d-70 standby current (power supply current) ttl level i cc2 ras = cas = v ih 1.5 ma cmos level ras = cas 3 v cc ?.2 v 0.2 refresh current #1 (average power supply current) *2 mb814405d-60 i cc3 cas = v ih , ras cycling; t rc = min ma mb814405d-70 hyper page mode current *2 mb814405d-60 i cc4 ras = v il , cas cycling; t hpc = min 70 ma mb814405d-70 65 refresh current #2 (average power supply current) *2 mb814405d-60 i cc5 ras cycling; cas -before-ras ; t rc = min ma mb814405d-70 battery back up current (average power supply current) MB814405D-60L i cc6 cas -before-ras ; t rc = 125 m s t ras = min to 1 m s v ih 3 v cc ?.2 v, v il 0.2 v m a mb814405d-70l refresh current #3 (average power supply current) mb814405d-60 i cc9 ras = cas 0.2 v self refresh 300 m a mb814405d-70 300 90 75 2.0 1.0 90 75 90 75 300 300 1000 1000
8 mb814405d-60/60l/-70/70l n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol mb814405d-60 mb814405d-70 unit min. max. min. max. 1 time between refresh std power t ref 16.4 16.4 ms low power 128 128 2 random read/write cycle time t rc 105 125 ns 3 read-modify-write cycle time t rwc 142 167 ns 4 access time from ras *6,9 t rac ?0?0ns 5 access time from cas *7,9 t cac ?5?0ns 6 column address access time *8,9 t aa ?0?5ns 7 output hold time t oh 0?ns 8 output hold time from cas t ohc 5?ns 9 output buffer turn on delay time t on 0?ns 10 output buffer turn off delay time *10 t off ?5?5ns 11 output buffer turn off delay time from ras *10 t ofr ?5?5ns 12 output buffer turn off delay time from we *10 t wez ?5?5ns 13 transition time t t 250250ns 14 ras precharge time t rp 40?5ns 15 ras pulse width t ras 60 100000 70 100000 ns 16 ras hold time t rsh 15?0ns 17 cas to ras precharge time *21 t crp 5?ns 18 ras to cas delay time *11,12,22 t rcd 20 45 20 50 ns 19 cas pulse width t cas 10 10000 15 10000 ns 20 cas hold time t csh 40?0ns 21 cas precharge time (normal) *19 t cpn 10?0ns 22 row address set up time t asr 0?ns 23 row address hold time t rah 10?0ns 24 column address set up time t asc 0?ns 25 column address hold time t cah 10?5ns 26 ras to column address delay time *13 t rad 15 30 15 35 ns 27 column address to ras lead time t ral 30?5ns 28 column address to cas lead time t cal 30?5ns 29 read command set up time t rcs 0?ns 30 read command hold time referenced to ras *14 t rrh 2?ns 31 read command hold time referenced to cas *14 t rch 0?ns 32 write command set up time *15 t wcs 0?ns 33 write command hold time t wch 10?0ns 34 we pulse width t wp 10?0ns 35 write command to ras lead time t rwl 15?5ns 36 write command to cas lead time t cwl 10?5ns
9 mb814405d-60/60l/-70/70l (continued) no. parameter notes symbol mb814405d-60 mb814405d-70 unit min. max. min. max. 37 din set up time t ds 0?ns 38 din hold time t dh 10?0ns 39 ras to we delay time t rwd 80?5ns 40 cas to we delay time t cwd 40?5ns 41 column address to we delay time t awd 50?0ns 42 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 43 cas set up time for cas -before- ras refresh t csr 0?ns 44 cas hold time for cas -before- ras refresh t chr 10?0ns 45 we set up time from ras *20 t wsr 10?0ns 46 we hold time from ras *20 t whr 10?0ns 47 access time from oe *9 t oea ?5?0ns 48 output buffer turn off delay from oe *10 t oez ?5?5ns 49 oe to ras lead time for valid data t oel 10?0ns 50 oe to cas lead time t col 0?ns 51 oe hold time referenced to we *16 t oeh 15?0ns 52 oe to data in delay time t oed 15?0ns 53 din to cas delay time *17 t dzc 0?ns 54 din to oe delay time *17 t dzo 0?ns 55 oe precharge time t oep 10?0ns 56 oe hold time referenced to cas t oech 5?ns 57 we precharge time t wpz 10?0ns 58 we to data in delay time t wed 15?5ns 59 ras to data in delay time t rdd 15?5ns 60 cas to data in delay time t cdd 15?5ns 61 ras to column address hold time t ar 45?0ns 62 write command hold time referenced to ras t wcr 45?0ns 63 data input hold time referenced to ras t dhr 45?0ns 64 hyper page mode read/write cycle time t hpc 25?0ns 65 hyper page mode read-modify- write cycle time t hprwc 73?5ns 66 access time from cas precharge *9,18 t cpa ?5?5ns 67 hyper page mode cas precharge time t cp 10?0ns 68 hyper page mode ras pulse width t rasp 200000 200000 ns 69 hyper page mode ras hold time from cas precharge t rhcp 35?0ns 70 hyper page mode cas precharge to we delay time t cpwd 55?5ns
10 mb814405d-60/60l/-70/70l notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih i cc1 , i cc3 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc4 is speci?d at one time of address change during one page cycle. *3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. *4. ac characteristics assume t t = 2 ns. *5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min) and v il (max). *6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig. 2 and 3. *7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *8. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *9. measured with a load equivalent to two ttl loads and 100 pf. *10. t off , t ofr , t wez and t oez is speci?d that output buffer change to high impedance state. *11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *12. t rcd (min) = t rah (min) + 2t t + t asc (min). *13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . *14. either t rrh or t rch must be satis?d for a read cycle. *15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *16. assumes that t wcs < t wcs (min). *17. either t dzc or t dzo must be satis?d. *18. t cpa is access time from the selection of a new column address (that is caused by changing cas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max) as shown in fig. 4. *19. assumes that cas -before-ras refresh. *20. assumes that test mode function. *21. the last cas rising edge. *22. the ?st cas falling edge.
11 mb814405d-60/60l/-70/70l n functional truth table x: ? or ? * : it is impossible in hyper page mode. operation mode clock input address input input data refresh note ras cas we oe row column input output standby h h x x high-z read cycle l l h l valid valid valid yes* t rcs 3 t rcs (min) write cycle (early write) l l l x valid valid valid high-z yes* t wcs 3 t wcs (min) read-modify- write cycle llh ? ll ? h valid valid valid valid yes* t cwd 3 t cwd (min) ras -only refresh cycle l h x x valid high-z yes cas -before-ras refresh cycle l l h x high-z yes t csr 3 t csr (min) hidden refresh cycle h ? l l h l valid yes previous data is kept test mode set cycle (cbr) l l l x high-z yes t csr 3 t csr (min) t wsr 3 t wsr (min) test mode set cycle (hidden) h ? l l l x valid yes t csr 3 t csr (min) t wsr 3 t wsr (min) fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad fig. 4 ? t cpa vs. t cp t rcd (ns) t rad (ns) t cp (ns) t rac (ns) t rac (ns) t cpa (ns) 60 ns version 70 ns version 140 120 100 80 60 20 40 60 80 100 120 70 ns version 100 90 80 70 60 10 30 40 50 60 40 50 80 70 60 50 40 10 20 30 40 50 60 30 60 ns version 70 ns version 60 ns 20 version
12 mb814405d-60/60l/-70/70l t asc fig. 5 ? read cycle description to implement a read operation, a valid address is latched by the ras and cas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. the access time is determined by ras (t rac ), cas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either oe or both ras and cas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 9 v ih v il dq (input) v ih v il oe ? or ? valid data t rc t ras t ar t rp t cdd t rcd t crp t asr t rah t cah t rch t rcs t dzc t oea t dzo t on t oed t oh t off t rad row add column add t ral t cal t aa t cac t rac high-z high-z t oh t csh t rsh t cas t on t rdd t wed t wez t oez t col t oel t wpz t rrh
13 mb814405d-60/60l/-70/70l fig. 6 ? early write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (input) a 0 to a 9 v oh v ol dq (output) description a write cycle is similar to a read cycle except we is set to a low state and oe is a ? or ? signal. a write cycle can be implemented in either of three ways ?early write, delayed write, or read-modify-write. during all write cycles, timing parameters t rwl , t cwl , t ral and t cal must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pins are latched with the falling edge of cas and written into memory. ? or ? t rc t ras t rp t csh t rcd t crp t cas t asr t rah t asc t cah high-z row add column add t wcr t wcs t wch t dh t ds valid data in t rsh t ar t dhr
14 mb814405d-60/60l/-70/70l fig. 7 ? delayed write cycle (oe controlled) ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description in the delayed write cycle, t wcs is not satis?d; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). ? or ? invalid data t rc t ras t rcd t crp t asr t cah t rcs t dzc t rp t asc t rah t cwl t wp t ds t dh t oed t dzo t oeh row add col add t wch t rwl high-z high-z high-z t on t on t ar t cas t csh t rsh t oez valid data i n
15 mb814405d-60/60l/-70/70l fig. 8 ? read-modify-write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. ? or ? t rwc t ras t rcd t crp t asr t cah t rwl t rcs t rp t asc t rah t cwl t ds t dh t oed t dzo t oeh row add col add t rad t cwd valid data t oez t oh t rwd t awd t dzc high-z t cac t rac t aa high-z high-z valid data i n t ar t on t on t oea t wp
16 mb814405d-60/60l/-70/70l t rch fig. 9 ? hyper page mode read cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. ? or ? valid data during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t ofr t rasp t asc t rcs t rhcp t rp t rcd row add col add t cas t rsh t hpc t cas t cas t cp t rch t rcs t rcs t dzc t cpa t cah t ar t cah t rah t asc t rrh t cah t asc t rch t cdd t on t cac t on t aa t rad col add col add t csh t ral high-z high-z t dzo t aa high-z t rac t rdd high-z t oh t oez t oed t cpa t oh t on t ohc t cac t ohc t oh t crp t asr t off
17 mb814405d-60/60l/-70/70l fig. 10 ? hyper page mode read cycle (oe controlled) ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. to obtain a high-impedance state, set oe or both ras and cas going high level. ? or ? valid data during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t rasp t asc t rhcp t rp t rcd row add col add t cas t rsh t hpc t cas t cp t dzc t cah t cah t rah t asc t rrh t cah t asc t rch t cac t aa t rad col add t ral high-z high-z t ofr high-z t off t oh t oez t oed t cac t oh t oh t aa t cpa t cac t aa t oea t oech t oep t oh t oea t dzo t on t rac t cp t cdd t ar t oez t col t oh t oea t oez t asr t crp t rcs t csh t cas t cal t cpa t rdd col add t on
18 mb814405d-60/60l/-70/70l fig. 11 ? hyper page mode read cycle (we controlled) ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (input) a 0 to a 9 v oh v ol dq (output) v ih v il oe description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. to obtain a high-impedance state, con?m either of the following conditions, oe set to a high level or we set to a low level after cas set to a high level or ras and cas set to a high level. ? or ? valid data during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t rasp t asc t rcs t rp row add col add t cas t rsh t hpc t cas t dzc t cah t rah t asc t cah t asc t rch t cac t aa t ral high-z high-z t off t oh t oez t oed t oh t oh t aa t cac t aa t oea t dzo t on t rac t ofr t rcs t rch t wpz t rch t wez t cac t on t wpz high-z t on t wez t wpz t cdd t wed t wez t on t ar t rcs t csh t rcd t cas t cah t rdd col add t rhcp t cal t crp t asr col add
19 mb814405d-60/60l/-70/70l t hpc fig. 12 ? hyper page mode early write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we dq (input) a 0 to a 9 v oh v ol dq (output) description the hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except we is set to a low state and oe is a ? or ? signal. data appearing on the dq pins is latched on the falling edge of cas and the data is written into the memory. during the hyper page mode write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. ? or ? during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t cas t rasp t crp t rp row add t rsh t rcd t csh t cas t asc t cah t asr col add col add high-z t cas t cp col add t cah t asc t cah valid data valid data t wcs t wch t wcs t wch t wcs t wch t ds t dh t asc t rah t ds t dh t ds t dh t ar t wcr t dhr t rhpc t cwl t cwl t ral t cwl t rwl valid data
20 mb814405d-60/60l/-70/70l fig. 13 ? hyper page mode delayed write cycle (oe controlled) description the hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the hyper page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). ? or ? invalid data dq (input) dq (output) ras cas we a 0 to a 9 oe valid valid col add col add row add data i n data i n high-z v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rasp t rp t cas t crp t csh t rcd t hpc t cp t rsh t cas t cwl t cah t asc t asc t cah t rah t asr t rwl t wch t cwl t wch t rcs t wp t wp t dh t dh t ds t ds t dzc t on t on t oed t oed t oeh t oez t oeh t oez t on t on t dzo
21 mb814405d-60/60l/-70/70l fig. 14 ? hyper page mode read/write mixed cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we a 0 to a 9 v oh v ol v ih v il oe description the hyper page mode performs read/write operations repetitively during one ras cycle. at this time, t hpc (min) is invalid. ? or ? valid data valid col add col add high-z row add high-z high-z data i n col add t rasp t hpc t crp t cp t rcd t cas t csh t rhcp t rsh t cas t cah t asc t ral t cah t rch t cas t asr t rad t asc t rah t cal t asc t cah t wcs t rp t rcs t wch t dzc t dzo t on t aa t rac t oea t cpa t dh t wed t wez t oed t aa t cac t on t ohc t oez t cac t ds
22 mb814405d-60/60l/-70/70l fig. 15 ? hyper page mode read-modify-write cycle v ih v oh description during the hyper page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. ? or ? valid data dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v il cas we a 0 to a 9 v ol v ih v il oe valid valid col add col add high-z row add t rasp t rwl t rp t ar t crp t rcd t hprwc t cp t rad t rah t asr t asc t cah t asc t cah t awd t rcs t cwl t wp t cpwd t rcs t cwl t wp t oeh t dh t ds t dh t ds t dzc t rwd t oed t oed t cac t cac t aa t aa t on t on t oez t oea t on t oeh t oez t dzo t rac t on t cpa t oea t cwd data data
23 mb814405d-60/60l/-70/70l fig. 16 ? ras -only refresh (we = oe = ? or ?? dq (output) ras v ih v il v ih v il v ih v il cas a 0 to a 9 v oh v ol description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 1,024 row addresses every 16.4-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and cas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, dq pins are kept in a high-impedance state. t rc ? or ? t rp t asr t rpc high-z t rah t crp t ras t off row address t crp t oh fig. 17 ? cas -before-ras refresh (addresses = oe = ? or ?? dq (output) ras v ih v il v ih v il cas v oh v ol description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if cas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in prep- aration for the next cas -before-ras refresh operation. we must be held high for the speci?d set up time (t wsr ) before ras goes low in order not to enter ?est mode? ? or ? t rc high-z t ras t rpc t cpn t csr t chr t rp t off t oh t csr t cpn t wsr t whr v ih v il we
24 mb814405d-60/60l/-70/70l column row address add valid data out high-z high-z valid data out high-z high-z fig. 18 ? hidden refresh cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il cas we a 0 to a 9 v oh v ol v ih v il oe description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of cas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. we must be held high for the speci?d set up time (t wsr ) before ras goes low in order not to enter ?est mode? ? or ? t rp t rc t ras v ih v il [normal mode] [test mode] v ih v il we dq (input) v oh v ol v ih v il oe v ih v il dq (output) t rc t ras t rp t oel t rcd t rad t rsh t chr t crp t asr t asc t rah t ral t cah t rcs t rrh t wsr t whr t aa t rac t dzc t cac t on t oh t off t oez t oed t oea t dzo t rcs t rrh t wsr t whr t aa t rac t dzc t cac t off t oh t on t oea t dzo t oez t oed
25 mb814405d-60/60l/-70/70l high-z description test mode; the purpose of this test mode is to reduce device test time to half of that required to test the device conventionally. the test mode function is entered by performing a we and cas -before-ras (wcbr) refresh for the entry cycle. in the test mode, read and write operations are executed in units of eights bits which are selected by the address combination of ca0. in the write mode, data is written into eight cells simultaneously. but the data must be input from all dq pins. in the read mode, the data of eight cells at the selected addresses are read out from dq and checked in the following manner. when the eight bits are all ? or all ?? a ? level is output. when the eight bits show a combination of ? and ?? a ? level is output. the test mode function is exited by performing a ras -only refresh or a cas -before-ras refresh for the exit cycle. in test mode operation, the following parameters are delayed approximately 5 ns from the speci?d value in the data sheet. t rc , t rwc , t rac , t aa , t ras , t csh , t ral , t rwd , t awd , t hpc , t hprwc , t cpa , t rhcp , t cpwd fig. 19 ? test mode set cycle (a 0 to a 9 , oe = ? or ?? ras v ih v il v ih v il v oh v ol v ih v il cas we d out ? or ? t rc t ras t rp t cpn t csr t chr t rpc t wsr t whr t off t oh
26 mb814405d-60/60l/-70/70l description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the functionality of cas -before-ras refresh circuitry. if, after a cas -before-ras refresh cycle. cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a 0 through a 9 are de?ed by the on-chip refresh counter. column address: bits a 0 through a 9 are de?ed by latching levels on a 0 to a 9 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows ; 1) normalize the internal refresh address counter by using 8 ras -only refresh cycles. 2) use the same column address throughout the test. 3) write ? to all 1,024 row addresses at the same column address by using normal write cycles. 4) read ? written in procedure 3) and check; simultaneously write ? to the same addresses by using cas -before-ras refresh counter test (read-modify-write cycles). repeat this procedure 1,024 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 1,024 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). fig. 20 ? cas -before-ras refresh counter test cycle dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il cas we a 0 to a 9 v oh v ol v ih v il oe ? or ? valid data high-z high-z high-z valid data in column address t chr t rp t csr t frsh t fcas t cp t ral t fcah t asc t wsr t whr t rcs t fcwd t cwl t rwl t wp t dh t ds t dzc t oed t fcac t on t oea t dzo t oeh t oez mb814405d-70 mb814405d-60 unit parameter min . max. ns no . min. max. 90 20 15 symbol (at recommended operating conditions unless otherwise noted.) cas to we delay time 91 10 ns 10 column address hold time cas pulse width 45 ns 40 15 ns 10 ns 15 20 access time from cas t fcac t fcah t fcwd t fcas t frsh ras hold time 92 93 94 note: assumes that cas -before-ras refresh counter test cycle only. ns 95 10 10 cas precharge time t cpt
27 mb814405d-60/60l/-70/70l high-z ? or ? description the self refresh cycle provides a refresh operation without external clock and external address. self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter. if cas goes to ? before ras goes to ? (cbr) and the condition of cas ? and ras ? is kept for term of t rass (more than 100 m s), the device can be entered the self refresh cycle. and after that, refresh operation is automatically executed per ?ed interval using internal refresh address counter during ?as =l and ?as =l? and exit from self refresh cycle is performed by toggling of ras and cas to ? with specifying t chs min. restruction for self refresh operation ; for self refresh operation, the notice below must be considered. 1) in the case that distribute cbr refresh are operated in read/write cycles self refresh cycles can be executed without special rule if 1,024 cycles of distribute cbr refresh are executed within t ref max. 2) in the case that burst cbr refresh or ras -only refresh are operated in read/write cycles 1,024 times of burst cbr refresh or 1,024 times of burst ras -only refresh must be executed before and after self refresh cycles. fig. 21 ? self refresh cycle (a 0 to a 9 = oe = ? or ?? ras v ih v il v ih v il v oh v ol v ih v il cas we d out t oh t cpn t rass t csr t wsr t whr t chs t rpc t rps t off 1,024 burst refresh cycle read/write operation t sn < 1 ms 1,024 burst refresh cycle read/write operation ras v ih v il t rass t ns < 1 ms * * * read/write operation can be performed non refresh time within t ns or t sn mb814405d-70 mb814405d-60 unit parameter min . max. no . min. max. 100 symbol (at recommended operating conditions unless otherwise noted.) ras precharge time 101 125 ns 105 ras pulse width cas hold time ?0 ns ?0 t rass t rps t chs 100 102 note: assumes self refresh cycle only. 100 m s self refresh operation
28 mb814405d-60/60l/-70/70l n package dimensions +0.05 C0.02 +.002 C.001 C.008 +.014 C0.20 +0.35 0.20 .008 .134 3.40 * 0.10(.004) 2.50(.098)nom details of "a" part 0.430.10(.017.004) 0.81(.032)max (.268.020) 6.810.51 r0.81(.032)typ 0.64(.025)min 2.25(.089)nom 26 22 18 14 13 9 5 1 index (.332.005) 8.430.13 (.300) nom 7.62 2.54(.100)typ 1.27(.050)typ 17.150.13(.675.005) 15.24(.600)ref "a" lead no 26-lead plastic leaded chip carrier (case no.: lcc-26p-m04) ? 1993 fujitsu limited c26054s-3c-1 notes: 1. *: this dimension includeds resin protrusion. (each side: .006 (0.15) max) 2. although this package has 20 leads only, its pin positions are the same as that of 26-lead package. dimensions in mm (inches)
29 mb814405d-60/60l/-70/70l all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan

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